Unfaithful Glitch Propagation in Existing Binary Circuit Models

We show that no existing continuous-time, binary value-domain model for digital circuits is able to correctly capture glitch propagation. Prominent examples of such models are based on pure delay channels (P), inertial delay channels (I), or the elaborate PID channels proposed by Bellido-D\'iaz et al. We accomplish our goal by considering the solvability/non-solvability border of a simple problem called Short-Pulse Filtration (SPF), which is closely related to arbitration and synchronization. On one hand, we prove that SPF is solvable in bounded time in any such model that provides channels with non-constant delay, like I and PID. This is in opposition to the impossibility of solving bounded SPF in real (physical) circuit models. On the other hand, for binary circuit models with constant-delay channels, we prove that SPF cannot be solved even in unbounded time; again in opposition to physical circuit models. Consequently, indeed none of the binary value-domain models proposed so far (and that we are aware of) faithfully captures glitch propagation of real circuits. We finally show that these modeling mismatches do not hold for the weaker eventual SPF problem.Comment: 23 pages, 15 figure

Metastability-Containing Circuits

In digital circuits, metastability can cause deteriorated signals that neither are logical 0 or logical 1, breaking the abstraction of Boolean logic. Unfortunately, any way of reading a signal from an unsynchronized clock domain or performing an analog-to-digital conversion incurs the risk of a metastable upset; no digital circuit can deterministically avoid, resolve, or detect metastability (Marino, 1981). Synchronizers, the only traditional countermeasure, exponentially decrease the odds of maintained metastability over time. Trading synchronization delay for an increased probability to resolve metastability to logical 0 or 1, they do not guarantee success. We propose a fundamentally different approach: It is possible to contain metastability by fine-grained logical masking so that it cannot infect the entire circuit. This technique guarantees a limited degree of metastability in---and uncertainty about---the output. At the heart of our approach lies a time- and value-discrete model for metastability in synchronous clocked digital circuits. Metastability is propagated in a worst-case fashion, allowing to derive deterministic guarantees, without and unlike synchronizers. The proposed model permits positive results and passes the test of reproducing Marino's impossibility results. We fully classify which functions can be computed by circuits with standard registers. Regarding masking registers, we show that they become computationally strictly more powerful with each clock cycle, resulting in a non-trivial hierarchy of computable functions

Diffusive clock synchronization in highly dynamic networks

International audienceThis paper studies the clock synchronization problem in highly dynamic networks. We show that diffusive synchronization algorithms are well adapted to environments in which the network topology may change unpredictably. In a diffusive algorithm, each node repeatedly (i) estimates the clock difference to its neighbors via broadcast of zero-bit messages, and (ii) updates its local clock according to a weighted average of the estimated differences. The system model allows for drifting local clocks, running at possibly different frequencies. We show that having a rooted spanning tree in the network at every time instance suffices to solve clock synchronization. We do not require any stability of the spanning tree, nor do we impose that the links of the spanning tree be known to the nodes. Explicit bounds on the convergence speed are obtained. In particular, our results settle an open question posed by Simeone and Spagnolini to reach clock synchronization in dynamic networks in the presence of nonzero clock drift. We also identify certain reasonable assumptions that allow for a significant higher convergence speed, e.g., bidirectional networks or random graph models

PALS: Distributed Gradient Clocking on Chip

Consider an arbitrary network of communicating modules on a chip, each requiring a local signal telling it when to execute a computational step. There are three common solutions to generating such a local clock signal: (i) by deriving it from a single, central clock source, (ii) by local, free-running oscillators, or (iii) by handshaking between neighboring modules. Conceptually, each of these solutions is the result of a perceived dichotomy in which (sub)systems are either clocked or asynchronous. We present a solution and its implementation that lies between these extremes. Based on a distributed gradient clock synchronization algorithm, we show a novel design providing modules with local clocks, the frequency bounds of which are almost as good as those of free-running oscillators, yet neighboring modules are guaranteed to have a phase offset substantially smaller than one clock cycle. Concretely, parameters obtained from a 15nm ASIC simulation running at 2GHz yield mathematical worst-case bounds of 20ps on the phase offset for a $32 \times 32$ node grid network

New transience bounds for long walks in weighted digraphs

International audienceWe consider the sequence of maximal weights of walks of lengt n between two fixed nodes in a weighted digraph. It is known that these sequences show a periodic behavior after an initial transient. We identify relevant graph parameters and propose a modular strategy to derive new upper bounds on the transient. To the best of our knowledge, our bounds are the first that are both asymptotically tight and potentially subquadratic. In particular, the new bounds show that the transient is linear in the number of nodes in bi-directional trees. Besides, our results enable a fine-grained performance analysis and give guidelines for the design of distributed systems based on max-plus recursions